A storage device which includes memory cells three-dimensionally arranged has been developed. For example, a NAND type storage device includes a plurality of stacked electrode layers with a semiconductor channel penetrating the stacked electrode layer. Memory cells are formed where the semiconductor channel intersect an electrode layer. The electrode layers function as a control gate of the memory cells. In a storage device having such a structure, it is necessary to lead out the electrode layers individually, that is provide connecting portions to electrically connect each electrode layer to a drive circuit or the like. For this reason, typically a structure is adopted in which ends of the plurality of electrode layers form in a staircase or stair-stepped pattern so that a vertical contact plug can be connected to each of the end portions. However, as the number of stacked electrode layers increases, the device layout area required for forming the end portions in a staircase pattern on the chip surface increases, which reduces then number of memory cells that can be formed in a device of a given size and/or hinders miniaturization of storage devices.